The constant drive toward miniaturization of semiconductor devices makes low equivalent oxide thickness dielectrics particularly desirable. The field of III-V MOS devices is no exception. However, when the equivalent oxide thickness is lowered, the tunnelling leakage current through the dielectric tends to get higher.
To tackle this problem, high-k dielectrics have been used. However, high-k dielectrics have a small bandgap, which can also contribute to high tunnelling leakage current. Furthermore, the decrease in equivalent oxide thickness should not be accompanied by a decrease in charge mobility in the III-V substrate. Indeed, this mobility may be particularly important in Field Effect Transistors.
US 2006/0054937 proposed addressing these issues by inserting between the substrate and the primary dielectric layer an oxide layer including a group III element from the substrate, and by further inserting between the oxide layer and the primary dielectric layer an interfacial dielectric layer. The interfacial dielectric layer includes HfO2, ZrO2, a zirconium silicate alloy, and/or a hafnium silicate alloy. This approach, however, may have the drawback of involving a relatively large number of layers, which multiplies the chances of defects at the interfaces. Also, the obtained equivalent oxide thickness is relatively large.